The present invention relates to a switching circuit.
A composite technique has been developed to form different kinds of elements in a single semiconductor substrate, to obtain a semiconductor integrated circuit having diverse functions and a high degree of integration.
For instance, a circuit technique for combining bipolar transistors with insulated gate-type fieldeffect transistors (hereinafter referred to as MOSFET's) has been disclosed in Japanese Patent Publication No. 43997/1972 and in Japanese Patent Laid-Open No. 26181/1977.
FIG. 1 shows a switching circuit which was contrived by the inventors of the present invention and in which a bipolar transistor and an insulated gate-type field effect transistor are combined. (See U.S. Pat. Ser. No. 513,056 which is hereby incorporated by reference.) The circuit shown in FIG. 1 is an input buffer circuit (switching circuit) used for, for example, in a Bi-CMOS (bipolar/CMOS mixed type) gate array. The circuit consists of two bipolar transistors Q1, Q2 that constitute an output stage, a CMOS inverter 12 which drives the bipolar transistor Q1 in an inverted manner, and a buffer amplifier (voltage follower) 14 which drives the other bipolar transistor Q2 in a non-inverted manner.
This circuit operates as described below. A logic signal applied to an input terminal IN is divided into two branches. One part of the input is phase inverted by the CMOS inverter 12 and is input to the base of the transistor Q1 of the output stage. The other part of the input is converted into a low impedance by the buffer amplifier 14 and is input in phase to the base of the other bipolar transistor Q2 of the output stage. Therefore, the two bipolar transistors Q1, Q2 in the output stage are rendered conductive and are driven in a complementary manner. When one transistor Q1 is ON (conductive) and the other transistor Q2 is OFF (nonconductive), a changing current is supplied to the load Co through the transistor Q1. When one transistor Q1 is OFF and the other transistor Q2 is ON, the electric charge stored in the load Co is discharged through the other transistor Q2. Accordingly, the capacitive load Co is driven in this fashion.
The switching circuit has the features (effects) described below.
(1) The CMOS inverter 12 and the buffer amplifier circuit 14 have nearly the same signal transmission speed; hence, the bases of the two transistors Q1, Q2 are driven nearly at the same timing in an opposite phase relation. Therefore, the two transistors Q1, Q2 are turned on simultaneously for only a short time, making it possible to decrease the through current.
(2) The two transistors Q1, Q2, which are of the npn-type, can be used to constitute the output stage. When a semiconductor integrated circuit is constructed, therefore, a high cut-off frequency f.sub.T can be easily obtained to realize a high operation speed.
(3) When the bipolar transistor Q1 in the output stage is turned off, the electric charge accumulated in the base thereof can be quickly extracted through a MOSFET M2 of the CMOS inverter 12. When the other bipolar transistor Q2 in the output stage is turned off, the electric charge accumulated in the base thereof can be quickly extracted by a low-impedance output of the voltage follower 14. That is, the two bipolar transistors Q1, Q2 in the output stage, respectively, have paths for effectively extracting the electric charge accumulated in the bases. Therefore, the switching time from ON to OFF is conspicously shortened.
(4) Since a power source terminal p1 of the voltage follower 14 is connected to the output terminal OUT, the discharging current of the capacitive load Co connected to the output terminal OUT flows not only to the other transistor Q2 in the output stage but also to the voltage follower 14 as an operation current from the first power source terminal p1. At the moment when the logic state of the buffer output OUT changes from "H" (high logic level) to "L" (low logic level), the electric charge stored in the load Co is allowed to discharge through the transistor Q2 and the voltage follower 14. Therefore, the driving power is greatly reinforced for the capacitive load Co, especially at the moment of breaking.
(5) Further, since the CMOS inverter 12 and the voltage follower 14 have high input impedances, there is obtained a high input impedance as viewed from the input side.
(6) The first power source terminal p1 of the voltage follower 14 is connected not to the power source V.sub.DD but to the collector (output terminal OUT) of the transistor Q2 of the output stage, and the base potential of the transistor Q2 is not higher than the collector potential thereof. Therefore, the transistor Q2 is not saturated.
The switching circuit exhibits excellent features as described above. Further study of the problem enabled the inventors to realize the switching circuit in the form of an integrated circuit. They have found that in designing constants for the circuit, many contrivances are necessary to satisfy the high-speed characteristics and the low power consumption that are strictly necessary for the switching circuit. The present invention was achieved through the above study.